A conventionally known lateral semiconductor device has an SOI (Silicon On Insulator) substrate formed of lamination of a semiconductor substrate, a buried oxide layer, and an active layer, and has a pair of main electrodes formed on the surface of the active layer. The lateral semiconductor device utilizing the SOI substrate is characteristically less prone to malfunction caused by a surge voltage, and is expected to be a promising semiconductor device.
An example of the above-described semiconductor device is disclosed by patent literature 1. FIG. 25 schematically shows a plan view of essential parts of a lateral n-type channel LDMOS (Laterally Diffused MOS) 1000 described in patent literature 1. FIG. 26 is a cross-sectional view of the LDMOS shown in FIG. 25 taken along line A-A. It should be noted that electrodes and field oxide layer shown in FIG. 26 are not shown in FIG. 25.
The LDMOS 1000 includes a semiconductor substrate 200 made of a single crystal silicon containing a p-type impurity in a high concentration, a buried oxide layer 300 made of silicon oxide (SiO2) and disposed on the semiconductor substrate 200, and an active layer 140 made of a single crystal silicon and disposed on the buried oxide layer 300.
The active layer 140 includes an n-type well semiconductor region 50, a p-type well semiconductor region 60, a surface semiconductor layer 70, a bottom semiconductor layer 80, an intermediate semiconductor layer 90, and a source semiconductor region 101.
The n-type well semiconductor region 50 is a semiconductor region surrounding an n-type drain semiconductor region 102. The p-type well semiconductor region 60 is a semiconductor region surrounding the n-type source semiconductor region 101.
The surface semiconductor layer 70 is formed in a part of the top surface of the active layer 140, and is interposed between the n-type well semiconductor region 50 and the p-type well semiconductor region 60. According to the plan view (see FIG. 25), the p-type well semiconductor region 60 and the surface semiconductor layer 70 are entirely isolated from each other. The surface semiconductor layer 70 contains a p-type impurity (typically boron). The surface semiconductor layer 70 is electrically connected to a source terminal S via a contact semiconductor region 70a. 
The bottom semiconductor layer 80 is formed in a part of the bottom surface side of the active layer 140, interposed between the n-type well semiconductor region 50 and the p-type well semiconductor region 60, and isolated by the intermediate semiconductor layer 90 from the surface semiconductor layer 70. The bottom semiconductor layer 80 has contact with the n-type well semiconductor region 50, and is isolated from the p-type well semiconductor region 60. The bottom semiconductor layer 80 contains an n-type impurity (typically phosphorus). The impurity concentration in the bottom semiconductor layer 80 decreases from its surface joining the buried oxide layer 300 toward its top surface.
The LDMOS 1000 includes the surface semiconductor layer 70, the intermediate semiconductor layer 90, and the bottom semiconductor layer 80, and accordingly, the critical voltage at an interface between the active layer 140 and the buried oxide layer 300 can be increased, and the breakdown voltage per unit thickness of the buried oxide layer 300 can be improved. The surface semiconductor layer 70, the intermediate semiconductor layer 90, and the bottom semiconductor layer 80 form a so-called RESURF (Reduced Surface Field) structure.
However, the semiconductor devices described in above patent literature 1 pose the following problems. That is, since the p-type well semiconductor region 60 and the surface semiconductor layer 70 are entirely isolated from each other as viewed in the plan view, current flows in the entire area between the p-type well semiconductor region 60 and the n-type well semiconductor region 50 in the plan view. Thus, in the n-type drain semiconductor region 102, a current amount per unit area increases (causing current crowding), and consequently the n-type drain semiconductor region 102 produces a high-temperature heat. As a result, a problem of deterioration in forward breakdown voltage of LDMOS 1000 has been posed. In particular, in the case of designing the LDMOS 1000 as a level-shifting device, the drain side is set as a high potential side, and thus a large amount of saturation current flows to the drain side. If such a large amount of saturation current flows, the current concentrates at the drain region, of which temperature is rising, and consequently the problem of deterioration in forward breakdown voltage is caused.
In addition, in order to set the surface semiconductor layer 70 and the source semiconductor region 101 to have the same electric potential, the contact semiconductor region 70a needs to be formed in the surface semiconductor layer 70. With this formation of the contact semiconductor region 70a, the dimensions of the LDMOS 1000 are increased, resulting in a problem of having difficulty in downsizing the LDMOS 1000.